YIELD,len,wid,excl,wfr,def,sel
Calculate gross and net die per wafer and yield

len         length of the die (stepping distance of the die in X) in mm
wid        width of the die (stepping distance of the die in Y) in mm
excl       size of the edge exclusion region in mm
wfr        diameter of the wafer in mm
def        defect density in defects/cm2
sel         number denoting the selected result.
              Use 1 gross die, 2 for net die and 3 for wafer yield

Notes

Use this form to calculate the gross die per wafer and net yield at the wafer level. The required parameters for calculating the gross die per wafer are the die size, the edge exclusion and the wafer size. The die size is the stepping distance on the wafer and not the size of the die after saw. If the sawn die size is known, add the saw alley width to calculate the die size. The edge exclusion is the region in the outer edges of the wafer that are left vacant to allow handling and to allow sealing of the wafer in the etch fixture for KOH etch or DRIE. It is usually around 5mm for KOH etched wafers while for DRIE etched wafer it is higher. The estimated die number does not include the area left out for including alignment targets or test sites. Also based on the die layout and how well the available wafer area is used, the die number may vary.

Based on the defect size and the area of the die, the wafer level yield can be estimated using the probability theory. Based on the estimated yield the net die per wafer is calculated.

The plot shows the dependence of the percentage yield on the size of the die for a given defect density. It shows that when the area of the die increases the yield that can be expected out of a wafer drops for a given defect density.

Assumptions

-The area lost to alignment marks, test sites and ECE contact are not included in the calculation of die number.
-Optimum utilization of the wafer area is assumed in the die layout.
-The estimated yield is based on the probability of defect distribution and is approximate.
-The yield is at the wafer level, there may be a further drop in yield after packaging.
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